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NXP Semiconductors
IP4790CZ38
DisplayPort protection
6.2 Pin description
Table 2.
Pin description
Symbol
VBIAS
GND
ML_0A
n.c.
GND
ML_1A
n.c.
GND
ML_2A
n.c.
GND
ML_3A
n.c.
GND
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
bias voltage
ground
main link 0A lane protection
not connected
ground
main link 1A lane protection
not connected
ground
main link 2A lane protection
not connected
ground
main link 3A lane protection
not connected
ground
n.c.
15, 16, 17, not connected
18, 19
IP4790CZ38_1
HOT_PLUG
AUX_B
AUX_A
n.c.
GND
ML_3B
n.c.
GND
ML_2B
n.c.
GND
ML_1B
n.c.
GND
ML_0B
n.c.
GND
BIAS_CAP
20
21
22
23, 24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Hot Plug signal protection
auxiliary channel B protection
auxiliary channel A protection
not connected
ground
main link 3B lane protection
not connected
ground
main link 2B lane protection
not connected
ground
main link 1B lane protection
not connected
ground
main link 0B lane protection
not connected
ground
capacitor bias (optional)
? NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2008
3 of 11
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